EDN

Accellera accepts Bluespec SystemVerilog donation

SANTA CRUZ, Calif. — Two language proposals from startup Bluespec Inc., provider of a SystemVerilog-based “assertion synthesis” tool, have been accepted by the Accellera standards organization for use ...
EDN

Bluespec synthesizes SystemVerilog verification assertions

Santa Cruz, Calif. – Claiming a new capability for chip designers, startup Bluespec Inc. this week will announce its ability to synthesize SystemVerilog verification assertions into Verilog 1995 RTL ...
Design-Reuse

Bluespec Updates ESL Synthesis Toolset; Offers Improved Verilog RTL Output for Practical IP Delivery Vehicle

WALTHAM, Mass.--May 11, 2006--Bluespec Inc. today released the latest version of its electronic system level (ESL) Synthesis software, offering a practical delivery vehicle for intellectual property ...
Design-Reuse

Bluespec Moves into Virtual Prototyping for Software Development, Hardware Validation

Bluesim, Bluespec ESL Synthesis Form Virtual Systems Platform for Modeling, Design WALTHAM, Mass. -- November 27, 2006-- Bluespec Inc., developer of the only ESL synthesis for control logic and ...